DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: SYSCLKT
Register Description: DS21Q55 TSYSCLK Pin Setting
Register Offset: 0x0013
Bit #
Name
Default
7
R4S1
0
6
R4S0
0
5
R3S1
0
4
R3S0
0
3
R2S1
0
2
R2S0
0
1
R1S1
0
0
R1S0
0
Bit 0 to 1: DS21Q55 Port 1 TSYSCLK Source (R1S0, R1S1)
The source for TSYSCLK 1 is Defined as shown in Table 4.
Bit 2 to 3: DS21Q55 Port 2 TSYSCLK Source (R2S0, R2S1)
The source for TSYSCLK 2 is Defined as shown in Table 4.
Bit 4 to 5: DS21Q55 Port 3 TSYSCLK Source (R3S0, R3S1)
The source for TSYSCLK 3 is Defined as shown in Table 4.
Bit 6 to 7: DS21Q55 Port 4 TSYSCLK Source (R4S0, R4S1)
The source for TSYSCLK 4 is Defined as shown in Table 4.
Table 4. TSYSCLKx Source Definition
RxS1, RxS0
00
01
10
11
TSYSCLK X CONNECTION
Drive TSYSCLK X with the 1.544MHz clock
Drive TSYSCLK X with the 2.048MHz clock
Drive TSYSCLK X with 8.192MHz clock
Drive TSYSCLK X with DS21Q55 Port X BPCLK
Register Name: SYSCLKR
Register Description: DS21Q55 RSYSCLK Pin Setting
Register Offset: 0x0014
Bit #
Name
Default
7
T4S1
0
6
T4S0
0
5
T3S1
0
4
T3S0
0
3
T2S1
0
2
T2S0
0
1
T1S1
0
0
T1S0
0
Bit 0 to 1: DS21Q55 Port 1 RSYSCLK Source (T1S0, T1S1)
The source for RSYSCLK 1 is Defined as shown in Table 5.
Bit 2 to 3: DS21Q55 Port 2 RSYSCLK Source (T2S0, T2S1)
The source for RSYSCLK 2 is Defined as shown in Table 5.
Bit 4 to 5: DS21Q55 Port 3 RSYSCLK Source (T3S0, T3S1)
The source for RSYSCLK 3 is Defined as shown in Table 5.
Bit 6 to 7: DS21Q55 Port 4 RSYSCLK Source (T4S0, T4S1)
The source for RSYSCLK 4 is Defined as shown in Table 5.
Table 5. RSYSCLKx Source Definition
TxS1, TxS0
00
01
10
11
RSYSCLK X CONNECTION
Drive RSYSCLK X with the 1.544MHz clock
Drive RSYSCLK X with the 2.048MHz clock
Drive RSYSCLK X with 8.192MHz clock
Drive RSYSCLK X with DS21Q55 Port X BPCLK
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